1. Field of the Invention
The present invention relates to a display panel driving circuit for driving a display panel, and in particular relates to a display panel driving circuit having an output part generating a push-pull output as a driving output for driving a display panel.
2. Description of the Related Art
A conventional display panel driving circuit is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 2005-192260.
FIG. 1 is a schematic circuit diagram showing a display panel driving circuit related to a display panel driving circuit according to the present invention. The display panel driving circuit of FIG. 1 is configured by a differential input part 10, a voltage signal generation part 20, and an output part 30.
The differential input part 10 includes p-channel metal oxide semiconductor (PMOS) transistors 11 and 12 having gate terminals to which an input inversion voltage VIN− and an input non-inversion voltage VIN+ are supplied respectively. Source terminals of the PMOS transistors 11 and 12 are connected to a node N11. The node N11 is connected to a positive power-supply voltage VDD via a PMOS transistor 13 having a gate terminal to which a bias voltage VP is supplied. The PMOS transistor 13 configures a constant-current circuit which provides a substantially constant electric current to the PMOS transistors 11 and 12.
Drain terminals of PMOS transistors 11 and 12 are connected to nodes N12 and N13, respectively. These nodes N12 and N13 are connected to a negative power-supply voltage VSS via N-channel metal oxide semiconductor (NMOS) transistors 14 and 15, respectively. Gate terminals of NMOS transistors 14 and 15 are connected to the node N12.
The voltage signal generation part 20 includes an NMOS transistor 21 having a gate terminal to which a voltage on the node N13 is applied. The NMOS transistor 21 has a drain terminal connected to a node N21 and a source terminal connected to the power-supply voltage VSS. The node N21 is connected to the power-supply voltage VSS via an NMOS transistor 22, and connected to the power-supply voltage VDD via a PMOS transistor 23. Gate terminals of the NMOS transistor 22 and 24 are connected to the node N21.
The NMOS transistor 24 has a source terminal connected to the power-supply voltage VSS and a drain terminal connected to a node N22. The node N22 is connected to the power-supply voltage VDD via a PMOS transistor 25, and connected to the node N12 via a phase compensation capacitor 26. The bias voltage VP is supplied to gate terminals of the PMOS transistors 23 and 25. The PMOS transistors 23 and 25 respectively configure constant-current circuits which flow respective electric currents to the NMOS transistor 22 and 24.
The output part 30 includes an NMOS transistor 31 having a gate terminal connected to the node N13, a source terminal connected to the power-supply voltage VSS, and a drain terminal connected to a node N31. The node N31 is connected to the power-supply voltage VDD via a PMOS transistor 32, and a gate terminal of the PMOS transistor 32 is connected to the node N22. The node N31 is connected to the node N13 via a phase compensation capacitor 33. An output voltage VOUT is supplied from the node N31 to an external load CL connected between the node N31 and the power-supply voltage VSS.
Operations of the circuit will now be described. The PMOS transistor 13 and the PMOS transistors 23, 25 configure constant-current circuits, respectively. An electric current flowing from the PMOS transistor 13 of the differential input part 10 is defined as i1. Electric currents flowing from the PMOS transistors 23 and 25 of the voltage signal generation part 20 are defined as i2 and i3, respectively.
A voltage state in which the input non-inversion voltage VIN+ is substantially same as the input inversion voltage VIN− is defined as a stationary state. In the stationary state, respective electric currents flowing from the PMOS transistors 11 and 12 of the differential input parts 10 are given by i1/2. Electric currents flowing from the NMOS transistors 21, 22, and 24 of the voltage signal generation part 20 are given by i2/a, i2/β, and i3, respectively, where a and β are any values at which the display panel driving circuit appropriately can operate and an equation given by (1/a)+(1/β)=1 is fulfilled. It is usually configured that i2 is equal to or larger than i3.
In response to a change from the stationary state to a voltage state in which the input non-inversion voltage VIN+ is higher than the input inversion voltage VIN−, in the differential input part 10, an electric current flowing from the PMOS transistor 11 increases, whereas an electric current flowing from the PMOS transistor 12 decreases. A voltage applied on the node N12 increases, whereas a voltage applied on the node N13 decreases. The voltage on the node N13 applied to the gate terminal of NMOS transistor 31 of the output part 30 decreases, thus decreasing an electric current (an electric current flowing from the external load CL to the node N31) flowing from the NMOS transistor 31.
At this time, in the voltage signal generation part 20, the voltage on the node N13 of the differential input part 10, which is also applied to the gate terminal of the NMOS transistor 21, decreases, thus decreasing an electric current flowing in the NMOS transistor 21. An electric current flowing to the NMOS transistor 22 increases, thus increasing a voltage on the node N21. An electric current flowing to the NMOS transistor 24 increases, thus decreasing a voltage on the node N22. Therefore, a charging current flowing from the PMOS transistor 32 of the output part 30 to the external load CL increases. In the voltage state in which VIN+ is higher than VIN−, the output voltage VOUT increases.
In response to a change from the stationary state to a voltage state in which the input non-inversion voltage VIN+ is lower than the input inversion voltage VIN−, on the other hands, in differential input part 10, the electric current flowing to the PMOS transistor 11 decreases, whereas the electric current of the PMOS transistor 12 increases. The voltage of the node N12 decreases, whereas the voltage on node N13 increases. The voltage increase on the node N13 turns off the NMOS transistor 31, thus increasing the electric current flowing from the external load CL to the NMOS transistor 31 of the output part via the node N31. The output voltage VOUT decreases in the voltage state in which VIN+ is lower than VIN−.
At this time, in the voltage signal generation part 20, the voltage increase on the node N13 turns on the NMOS transistor 21, thus increasing the electric current flowing to the NMOS transistor 21 and decreasing the electric current flowing from the NMOS transistor 22. The voltage of node N21 decreases. Since the electric current flowing to the NMOS transistor 24 also decreases, the voltage on the node N22 increases. A charging current supplied from the PMOS transistor 32 of the output part 30 to the external load CL decreases. In the voltage state in which VIN+ is lower than VIN−, the output voltage VOUT decreases.
Thus, the output voltage VOUT corresponding to a difference in voltage between the input non-inversion voltage VIN+ and the input inversion voltage VIN− is supplied to the external load CL.
However, there is the following difficulty in the display panel driving circuit of FIG. 1. The output part 30 is configured by the NMOS transistor 31 and the PMON transistor 32 which are push-pull connected to each other. The NMOS transistor 31, which is one of the push-pull connection, is directly controlled by an output signal of the differential input part 10 (the voltage on the node N13), and the PMON transistor 32, which is the other of the push-pull connection, is controlled by an output signal of the voltage signal generation part 20 (the voltage on the node N22).
In response to the change from the stationary state into the voltage state where the input inversion voltage VIN− is lower than the input non-inversion voltage VIN+, the voltage increase on the node N13 immediately drives the NMOS transistor 31 of the output part 30, thus immediately decreasing the output voltage VOUT. In response to the change from the stationary state into the voltage state where the input inversion voltage VIN− is lower than the input non-inversion voltage VIN+, on the other hand, the voltage decrease of the node N13 decreases the voltage on the node N22 of the voltage signal generation part 20 and drives the PMOS transistor 32 of the output part 30, thus increasing the output voltage VOUT. The display panel driving circuit generates the output voltage VOUT at different response speeds when the output voltage VOUT increases and decreases. The response speed when the output voltage VOUT increases is slower than that when the output voltage VOUT decreases, which causes distortion in waveform of the output signal and timing errors.
Typical solutions improves the problems by increasing the electric current of constant-current circuits configured by the PMOS transistors 13, 23, and 25 and by increasing a gm (a coefficient of mutual induction) of the PMOS transistor 32 of the output part 30. However, the solutions increase electric current consumption and a circuit area.
It is an object of the present invention to provide a display panel driving circuit having output part for generating a push-pull output as a driving output for driving a display panel and generating the push-pull output whose response speed is well balanced when the push-pull output increases and decreases without increase electric current consumption and a circuit area thereof.